Generally, in packet-based high speed serial communication, a multi-lane is used for expanding a total bandwidth, and one packet is distributed to a plurality of lanes and transmitted.
For example, a packet format of the peripheral component interconnect (PCI) express protocol is as illustrated in FIG. 1A, and when a computer transmits the PCI express packet distributed to a quadruple lane, the PCI express packet is transmitted and received in a format illustrated in FIG. 1B.
However, when data is distributed by lanes and transmitted, a skew between the lanes occurs due to an electrical characteristic and interference, and thus, the order where the distributed data reaches a destination is changed.
To solve such a problem, a related art receiver uses a logic which removes a skew between lanes and aligns a packet, for normally restoring the packet.
Moreover, the related art receiver cannot restore for itself a packet where a skew occurs, and periodically receives, from a transmitter, a packet for inter-lane alignment for each lane.
In a related art method, the related art receiver recognizes one of a plurality of lanes as a reference lane and aligns data, which precedes or succeeds the reference lane, in a buffer which is provided for each lane, thereby restoring a normal packet.
However, in the related art method, when a data skew deviates from a depth of the buffer for each lane, all lanes are put in an incommunicable state, and thus, it is required to again initialize all the lanes. For this reason, a data packet cannot be transmitted and received for a considerable time.
In addition, when one of lanes other than the reference lane is permanently put in an inoperable state due to a fault, available lanes cannot be sometimes used despite all the lanes being initialized.
For example, a device which uses a PCI express link (where the link is a unit where a packet is transmitted and received by using all lanes) consisting of four lanes 0 to 3 will now be described. When the lane 3 of the device is permanently put in an inoperable state, despite the lanes 0 to 2 being available, only two the lanes 0 and 1 are used. Also, when the lane 2 is permanently put in an inoperable state, despite the lanes 0, 1 and 3 being available, only the two lanes 0 and 1 are used. Likewise, when the lane 1 is permanently put in an inoperable state, despite the lanes 0, 2 and 3 being available, only one the lane 0 is used. Also, when the lane 0 which is a reference lane is permanently put in an inoperable state, despite the lanes 1 to 3 being available, all the lanes cannot be used, and for this reason, an overall system is sometimes stopped.
Therefore, the related art method is not suitable for, particularly, a system requiring high availability.
Moreover, in a related art transmission and reception apparatus, normal operations of two devices which access each other are ensured when the same lanes access each other. In detail, in a high speed serial communication link consisting of four lanes 0 to 3, a normal operation is ensured when the lane 0 accesses a correspondent lane 0, the lane 1 accesses a correspondent lane 1, the lane 2 accesses a correspondent lane 2, and the lane 3 accesses a correspondent lane 3.